AMD Layoffs 2026: Where Semiconductor Talent Is Going

AMD Layoffs 2026: Where Semiconductor Talent Is Going

AMD ran a single ~1,000-person reduction in late 2024 (about 4 percent of a 26,000-person base) and has been net-hiring engineering talent through 2026, with the larger semiconductor layoff story belonging to Intel (25,000+ positions cut), VMware-Broadcom, and the Confluent and Snowflake data-platform reset. The small AMD displacement pool that has actually surfaced sits mostly in Santa Clara, Austin, and Markham, while the absorbing destinations on the desk this year are Nvidia first, Apple silicon second, then Broadcom and Marvell custom ASIC, the hyperscaler in-house silicon teams (Google TPU, AWS Trainium, Microsoft Maia, Meta MTIA), and the RISC-V and AI accelerator startup tier (Tenstorrent, Rivos, MatX, Etched, Cerebras, SambaNova, Groq).

Last updated: May 23, 2026

Tom Kenaley, KORE1. I run the technical staffing desk and most of my placement work for the past eighteen months has been chip-side. RTL, verification, physical design, firmware, silicon validation, FPGA. I’m writing this because the search trend is real and the answer most candidates and hiring managers are getting from the press doesn’t match what the desk sees from week to week. KORE1 earns a placement fee when companies hire semiconductor talent through our semiconductor staffing practice. So my interest aligns with candidates getting an honest read on what’s moving in the market. Factor that in.

The short version. AMD is not the layoff story of 2026. AMD is the company every other semiconductor company’s displaced talent is trying to land at, alongside Nvidia and the AI accelerator startups. The reason “AMD layoffs 2026” gets typed into Google is mostly residual traffic from the November 2024 announcement, mixed with a handful of small Q1 2026 attrition events that Blind picked up. The bigger story is Intel, and the second-biggest story is the AI-era reshuffle inside data infrastructure. We covered both in Intel Layoffs 2026 and Databricks Layoffs 2026 if you want the neighborhood. This piece is about AMD’s slice and the talent map it implies.

What AMD Actually Did

Public record, in order.

November 15, 2024. AMD announced it would reduce headcount by approximately 4 percent. That worked out to roughly 1,000 positions against a 26,000-employee base. The company framed it as a realignment toward its “largest growth opportunities,” which everyone reading between the lines understood to mean Instinct AI accelerators and the EPYC server CPU line. Lisa Su’s third-quarter call the prior month had posted an 18 percent year-over-year revenue jump. So this was not a company in crisis. This was a company choosing where it wanted to bet for the next product cycle.

The 4 percent didn’t land evenly. Marketing took a disproportionate trim. Parts of the Radeon consumer GPU organization got pulled inward as the company reduced investment in discrete client graphics. Some Xilinx-acquired roles in the adaptive computing group consolidated. Senior individual contributors in core RTL, physical design, packaging, and validation were largely untouched, because the company knows exactly how scarce those profiles are in the broader market and what it would cost to rebuild that talent two cycles from now if they let it walk out the door this cycle.

August 2024 through May 2025. AMD acquired ZT Systems for $4.9 billion, picking up roughly 1,000 systems engineers focused on rack-scale and cluster-scale AI infrastructure, then six months later announced it would sell off ZT Systems’ physical manufacturing arm to Sanmina for $3 billion while keeping the engineering staff and shedding the assembly lines. That divestiture closed October 27, 2025. From a layoff-search-trend perspective, the headlines about ZT Systems and Sanmina caused some confusion in 2025. People read “AMD sells off ZT” and assumed it meant headcount cuts. It mostly didn’t. Over 1,000 ZT engineers stayed inside AMD and now sit underneath the Instinct rack-cluster roadmap.

Q1 2026. A small set of position eliminations surfaced on Blind and TheLayoff.com out of Markham, Santa Clara, and Austin. None hit WARN thresholds. Cross-checking the affected posters suggests fewer than 200 positions total across product management, business operations, and a few specific Radeon teams. Calling that a “2026 layoff” stretches the term past where most labor reporters draw the line, but it’s enough volume to keep the search query alive.

What didn’t happen. No companywide WARN filing. No earnings-call commitment to a workforce reduction target. No commentary from Lisa Su about cost cuts. The 2026 AMD posture, in the language of the 10-K and the Q1 FY2026 earnings letter, reads as “selective investment in AI and data center, ongoing efficiency.” That phrasing has not shifted in any material way across the last four quarters, and most sell-side analysts now read it as a statement that AMD is choosing to defend and extend its current engineering footprint rather than pull it back.

The Adjacent Semiconductor Layoff Picture

Most of what people are reacting to when they search “AMD layoffs 2026” is the broader chip-industry reset. Here’s the cohort.

Read the column on the right. Most of the displacement is concentrated in two players: Intel and the Broadcom-owned VMware stack. AMD is in the middle of the table, behaving more like Nvidia than like Intel. That’s the part the search term hides.

One thing worth saying out loud. Per the SIA 2026 workforce blueprint, 115,000 net new US chip jobs are projected through 2030 and roughly 67,000 of those positions sit at high risk of going unfilled. Constrained on the technician and engineering side. Which is to say, even when a name-brand chip company runs a reduction, the absolute count of qualified senior IC designers in the country does not get larger. It mostly gets moved.

Where Displaced AMD Engineers Are Going

This is the question candidates are asking and the question hiring managers should be asking. Here’s the pattern from the placements and outreach the desk has worked since November 2024.

Nvidia

The single biggest absorber of senior AMD engineering talent. By a wide margin. The competitive dynamic does the work here. Blackwell shipped against Instinct. The next two Nvidia architectures will too. So the profiles Nvidia weighs heaviest in candidate review (senior architects with HBM bandwidth tradeoffs in their heads, NVLink-versus-Infinity-Fabric topology experience, the GPU SoC integration muscle the Radeon Technologies Group has been growing since the Vega era) are exactly the profiles AMD spent years putting through tape-out cycles.

Comp deltas. A senior AMD GPU architect making $310,000 to $350,000 total comp will typically clear $480,000 to $620,000 at Nvidia once equity is normalized to the current valuation, assuming the move is L5 to L5 with no functional change in scope and no relocation arbitrage. Some land considerably higher. The Nvidia L5 median sits around $410,000 total comp per Levels.fyi as of mid-May; the AMD equivalent L5 median is closer to $250,000. That delta is the single most consequential number in chip-industry talent right now, and it is the reason AMD has been visibly raising its own bands at the L5 and L6 level over the past two cycles.

Apple silicon

Cupertino, Munich, Israel, and Austin. Apple has been quietly absorbing senior AMD packaging engineers and a smaller stream of CPU architects since 2023, with the M-series silicon team and the rumored Mac Pro server SKU as the destination roadmap and a hiring posture that prefers individual sourcing over recruiter introductions. Apple does not publish open req counts and does not engage with recruiters in the same way most of the cohort does, but the placement signal from candidate outreach is consistent: Apple is in on every senior packaging and advanced-node CPU resume that hits the market.

Broadcom and Marvell custom silicon

Different from the VMware side of Broadcom. The semiconductor side. Broadcom’s custom ASIC business serving Google TPU and Meta MTIA has been the most-overlooked talent magnet of the past two years. Marvell’s custom silicon practice for AWS Trainium and Microsoft Maia plays the same role on a smaller scale. Both companies are bidding aggressively for senior physical design and DFT engineers. Exactly the profiles AMD has trimmed lightly in 2025 and 2026. Exactly the profiles displaced from Intel’s Hillsboro reductions.

Hyperscaler in-house silicon teams

Google TPU (Mountain View, plus the smaller Madison team). AWS Annapurna Labs (Austin and Cupertino). Microsoft Maia and Cobalt (Redmond, with a growing Bay Area presence). Meta MTIA (Menlo Park). These four teams collectively run several hundred open requisitions at any moment and have hired AMD engineers steadily through 2024, 2025, and into 2026. The Microsoft Maia team in particular has picked up multiple senior AMD ML systems engineers as it accelerates the second-generation accelerator roadmap.

RISC-V and AI accelerator startups

The most interesting category on the list and the one most likely to be ignored by mainstream press coverage of layoffs.

Tenstorrent. Jim Keller’s company. Keller spent years at AMD twice, once on Zen and once on K8, and his current company employs a remarkable number of his former direct reports. Tenstorrent is hiring aggressively in Austin, Toronto, Bangalore, and Belgrade. Senior RTL designers with high-end CPU experience are the priority.

Rivos. Founded by ex-Apple and ex-AMD architects. RISC-V data-center CPU play. Mountain View headquarters with a Bangalore engineering site. The company quietly raised additional growth funding in late 2025 and has been net-hiring through Q1 and Q2 2026.

MatX. Smaller, Bay Area, RISC-V plus inference accelerator. Has picked up a handful of senior AMD engineers, mostly on the verification and physical design side.

Etched. Sohu transformer ASIC. Cupertino. Pulls a different profile than the RISC-V cohort, leaning more on the AI accelerator architecture side, but is on the destination map.

Cerebras, SambaNova, Groq. Wafer-scale, RDU, and inference-optimized respectively. All three have hired smaller numbers of senior AMD architects and verification leads, mostly in the past eighteen months.

The pattern across the startup tier reads the same way week after week and is worth naming explicitly before a senior candidate signs anything. They cannot match Nvidia or Apple on cash. They compete on equity upside and on the chance to ship a clean-sheet architecture without the legacy compatibility burden AMD has to carry on the x86 side and that Nvidia carries in a different shape on CUDA. The candidates who actually land in this tier are usually motivated by the second factor, not the first.

AMD Compensation in 2026, Honestly

If you’re a hiring manager trying to attract AMD-trained talent, or a candidate trying to figure out what to ask for, the bands matter. Levels.fyi data as of May 2026, cross-checked against Blind, Glassdoor, and what the desk has been seeing on closed offers.

Two things to read off that table.

The L5-to-L7 delta against Nvidia is wider than most candidates realize. Pick a senior IC designer at AMD with seven years in the company. Most of them have never sat down and actually benchmarked their package against the Nvidia equivalent. The desk has had multiple conversations this quarter where the candidate’s hesitation about moving turned out to be relocation cost, school district worry, partner’s commute, anything but the cash differential, because they had not run the comparison and assumed the gap was smaller than it actually is. Not the comp. They didn’t know about the comp.

The BLS May 2024 OES dataset for electronics engineers (excluding computer) showed a national median of $119,580. AMD pays its L3 entry band roughly 1.5x that. The L5 median lives at more than twice. The chip industry has its own gravity that has very little to do with what BLS publishes as the broader category mean.

For the Austin specifics, where AMD has its second-largest US engineering presence after Santa Clara, Glassdoor shows the Engineering Department average around $145K. That number is heavily pulled down by software roles. The hardware-only band is closer to $180K to $290K for L4 to L5. Our 2026 electrical engineer salary guide has wider bands for the rest of the analog and power side of the field if that’s the closer-fit reference for your search.

Geographic Picture in 2026

AMD has roughly 26,000 employees globally. The US concentration sits in Santa Clara HQ and Austin, with Markham (Ontario) carrying the next-largest North American site and Bangalore and Hyderabad carrying the largest non-US engineering footprint. Smaller sites in Boston, Orlando, San Diego, Fort Collins, Boxborough, and Bellevue. International sites in Cambridge UK, Munich, Stockholm, Shanghai, Beijing, Tokyo, Seoul, Sydney, Markham. Most of the 2024 reductions hit the US sites disproportionately. The 2026 Q1 attrition was concentrated in Santa Clara, Markham, and Austin, with smaller Bangalore movement.

Where the absorbed talent is landing geographically. A pattern.

Austin absorbs the most. Not even close, this year. The city has quietly assembled the densest concentration of advanced-node chip engineering hiring outside the Bay Area. Apple’s campus. Tesla’s Dojo and Hardware Engineering. Tenstorrent. Annapurna Labs. The satellite NXP and Cirrus Logic engineering sites. All of them work the same senior IC bench. Austin is where a senior physical design engineer can change companies without changing schools, which makes it the single market where chip-side mobility happens fastest. Our Austin IT staffing team works most of the hardware bench across these companies. The Phoenix metro is the second-heaviest, mostly because of TSMC Fab 21 ramping 4nm and 3nm and the Intel Ocotillo displacement flow we covered in the Intel layoffs piece.

San Jose and the broader Bay Area absorb most of the architecture and verification flow. Nvidia, Google TPU, Apple, Cerebras, MatX, Rivos. The Bay is where senior-level comp upgrades happen. San Jose IT staffing sees most of the senior IC architect movement in real time.

Markham and Toronto absorb the displaced Canadian RTG talent into Tenstorrent, Cohere’s hardware-adjacent recruiting, and the AMD-to-Apple Toronto migration that’s been running quietly for two years.

Bangalore is its own market. The 2026 displacement that surfaced there mostly recycled into Qualcomm, Marvell, and a handful of India-headquartered AI silicon startups. Equity is less of a factor in the India market than in the US, so cash compensation drives more of the decision and the moves tend to be lateral.

If You’re Hiring Semiconductor Talent in 2026

A few things the desk has been telling clients. Take them or argue with them.

Move on senior RTL and DV bench when it surfaces. The window between an AMD or Intel senior verification engineer becoming available and signing somewhere else is now 2 to 5 weeks, down from 10 to 14 just two years ago, because Nvidia, Apple, and the hyperscaler in-house teams have pre-built sourcing pipelines on these names and move on them within days of a LinkedIn status change. If your interview loop is six weeks long with two rounds of panel and an onsite, you will not win this bench. Tighten or lose.

Compete on the architecture, not the comp. You probably cannot match Nvidia or Apple on cash. The startups that are landing senior talent right now are selling clean-sheet architecture, IP ownership, and the chance to ship something that isn’t a third revision of a legacy product line. That story works when it’s true. It does not work when the engineer figures out within two weeks that they’re being asked to incrementally extend someone else’s roadmap.

Hire for the next two nodes, not the last two. The displaced talent that’s gettable in 2026 mostly has 5nm, 4nm, and 3nm tape-out experience. Some have 2nm exposure through Intel or TSMC partnerships. If your design is on 7nm because the team you bought in 2022 only had 7nm exposure, you are buying a delayed talent transition. Plan for it.

Don’t undervalue FPGA and adaptive-computing exposure. The Xilinx-acquired piece of AMD has a quieter talent pool that often gets overlooked in favor of CPU and GPU profiles. Versal-experienced engineers are unusually good at the kind of hardware-software co-design AI accelerator startups need at the system level. We covered the broader FPGA hiring picture in our 2026 FPGA hiring guide.

For the firmware and embedded layer that sits underneath the silicon, the pool moves slower than the IC bench because the candidates are more geographically rooted, the projects have longer ramp curves before someone is independently productive, and the comp bands don’t carry the kind of equity premium that incentivizes a cross-country move for a senior RTL engineer. Our firmware engineer staffing and embedded systems engineer staffing practices work that bench across Austin, Bangalore, Cambridge UK, and the smaller Boston-area pool.

For ASIC design specifically, the most contested profile in the market, our ASIC design engineer staffing page walks through the seniority bands and how we work the senior IC bench across Santa Clara, Austin, Hillsboro, and Phoenix.

Common Questions

Did AMD lay off employees in 2026?

A small number. Under 200 positions across Q1 2026 surfaced on Blind and TheLayoff, mostly in Markham, Santa Clara, and parts of the Radeon and business-operations groups. No companywide announcement and no WARN filing.

The 1,000-person reduction most articles reference happened in November 2024 and was a single event. The 2026 attrition is small enough that most layoff trackers do not record it as a discrete action.

Is AMD still hiring?

Aggressively, in specific groups. The careers site listed 800-plus open requisitions through May 2026, concentrated in Instinct AI accelerator design, EPYC server CPU teams, and the ZT-acquired rack-cluster systems engineering group.

Field roles, sales engineers, and software engineering around the ROCm stack are also active. The hiring posture is selective by group rather than across-the-board. Don’t read “AMD has 800 open reqs” as “AMD is desperate for any chip engineer.” A lot of those roles are tightly scoped.

Where are AMD engineers going if they leave?

Nvidia first, by a wide margin. Apple silicon second. Broadcom and Marvell custom silicon teams third. Hyperscaler in-house teams (Google TPU, AWS Trainium, Microsoft Maia, Meta MTIA) fourth. AI accelerator and RISC-V startups (Tenstorrent, Rivos, MatX, Etched, Cerebras, SambaNova, Groq) fifth.

Comp deltas favor moving for L5 and above. Below L5 the cash math is less compelling and the moves are usually driven by architecture interest or geography.

How much does an AMD senior engineer make in 2026?

L5 senior hardware engineer median sits around $250K total comp, with a range from roughly $225K to $310K depending on Santa Clara versus Austin, GPU versus CPU domain, and equity-vest year.

L6 staff engineers land in the $310K to $475K range. L7 senior staff and architects clear $475K to $711K at the Senior Fellow ceiling. Nvidia, Apple, and Broadcom pay materially more at every level above L4.

What’s the difference between Intel and AMD layoffs in 2026?

Scale and direction. Intel has cut more than 25,000 positions across three phases since late 2024 and is targeting a 75,000 worldwide headcount. AMD ran one 4 percent reduction in November 2024 and is now net-hiring engineers, with under 200 small 2026 attrition events.

The displaced Intel pool is concentrated in Hillsboro, Chandler, Folsom, and Santa Clara. The AMD pool, where it exists, is smaller and concentrated in Markham and Austin. Both pools largely get absorbed by the same destinations (Nvidia, Apple, hyperscaler in-house teams, AI accelerator startups), but the Intel volume is roughly 50 times larger.

Should I take an AMD offer in 2026?

Wrong question, slightly. The right question is which AMD group, which level, and what’s the equity vest schedule against the current share price.

An L5 RTL or DV offer with a strong Instinct or EPYC team and a fresh vest is competitive in absolute terms even though it’s behind Nvidia on cash, because the product roadmap has shipping leverage and the team is one of the few in the industry actually building something Nvidia has to react to. An L4 Radeon offer with a thin vest is a different story. Group matters more than the company name on the badge.

Is there a semiconductor talent shortage in 2026?

Yes, at the senior engineering and technician layer. The SIA’s 2026 workforce blueprint projects 67,000 of the 115,000 net new positions through 2030 are at risk of going unfilled, with the gap heaviest on technicians and physical design and verification engineers.

Layoffs at name-brand companies do not solve this. They redistribute the existing pool. The actual gap is upstream: not enough degree-program graduates in semiconductor disciplines, not enough technician training pipelines, and not enough of the senior cohort entering the next 10 years of their career rather than retirement.

Working the AMD-Adjacent Bench With KORE1

If you’re a hiring manager working an Instinct-, EPYC-, Radeon-, Xilinx-, or hyperscaler-adjacent search and the bench you’ve sourced internally has thinned, that’s the kind of search our semiconductor staffing practice was built to handle: senior IC profiles, advanced-node tape-out exposure, often a passive candidate who is not actively interviewing but who will pick up the phone for the right team if the conversation is run respectfully and the interview loop is not insulting in length. The Markham, Austin, and Santa Clara IC bench has more usable senior profiles available in 2026 than it has had in three years. Mostly because of Intel’s volume, not AMD’s. Reach out to our team and we’ll walk you through which profiles are actually available this quarter versus what the press coverage is implying.

If you’re an AMD engineer reading this and considering your next move, the candidate side of the practice covers the same names (Nvidia, Apple silicon, Broadcom custom ASIC, Marvell, Tenstorrent, Rivos, MatX, the hyperscaler in-house teams), and a quiet message gets a quiet response.

The 17-day average time-to-hire we publish company-wide is closer to 22 days on the senior IC bench, because the interview loops are longer in this category. That’s the honest number. The 17 average covers everything we place across IT, engineering, finance, healthcare IT, biomedical, creative, HR, and light industrial; the chip-side senior bench is one of the slower categories.